1. Technical Field
The present invention relates to an apparatus and a method for removing a DC offset in a power meter. More particularly, the present invention relates to an apparatus and a method for appropriately removing a DC offset in a power meter according to a pattern of an input signal.
2. Description of the Related Art
A power meter receives a voltage and current signal to calculate power. The voltage and current signal is an analog signal and is therefore converted into a digital signal using an analog-digital converter (ADC). A DC offset is generated during a process of converting the analog signal into a digital signal and therefore, errors occur in calculating power. Therefore, DC component may be removed using a high pass filter (HPF) or a DC removal logic in a voltage channel and a current channel.
In the related art, a method of multiplying an output signal from the ADC by a gain and then, passing the multiplied output signal through an HPF to remove the DC offset has been used. The current and voltage used in the power eter are generally a sinusoidal wave of 50 Hz or 60 Hz and an average value of the sinusoidal wave is generally ‘0’. Therefore, when there is the DC offset, the DC offset may be removed using the HPF or the DC removal logic. However, when a half-wave rectified signal that is a non-sinusoidal wave having, for example, a DC offset of 0.2, the DC offset of 0.2 is removed, but a distorted signal waveform appears due to the HPF.